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3.3V Single-Piece 4Mb Nonvolatile SRAM
with Clock
SRAM Read Mode
The DS3050W executes an SRAM read cycle whenever
CS (RTC chip select) and WE (write enable) are inactive
(high) and CE (SRAM chip enable) is active (low). The
unique address specified by the 19 address inputs (A0
to A18) defines which of the 524,288 bytes of SRAM data
is to be accessed. Valid data will be available to the
eight data output drivers within t ACC (access time) after
the last address input signal is stable, providing that CE
and OE (output enable) access times are also satisfied.
If CE and OE access times are not satisfied, then data
access must be measured from the later occurring sig-
nal ( CE or OE ) and the limiting parameter is either t CO for
CE or t OE for OE rather than address access.
SRAM Write Mode
The DS3050W executes an SRAM write cycle whenever
CS is inactive (high) and the CE and WE signals are
active (low) after address inputs are stable. The later-
occurring falling edge of CE or WE determines the start of
the write cycle. The write cycle is terminated by the earlier
rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the
high state for a minimum recovery time (t WR ) before
another cycle can be initiated. The CS and OE control
signal should be kept inactive (high) during SRAM write
cycles to avoid bus contention. However, if the output dri-
vers have been enabled ( CE and OE active) then WE dis-
ables the outputs in t ODW from its falling edge.
Clock Operations
Table 2. RTC Register Map
ADDRESS
B7
B6
B5
B4
DATA
B3
B2
B1
B0
FUNCTION/RANGE
xxxxFh
10 YEAR
YEAR
YEAR
00 – 99
xxxxEh
xxxxDh
X
X
X
X
X
10 M
10 DATE
MONTH
DATE
MONTH
DATE
01 – 12
01 – 31
xxxxCh
xxxxBh
X
X
FT
X
X
10 HOUR
X
X
DAY
HOUR
DAY
HOUR
01 – 07
00 – 23
xxxxAh
xxxx9h
X
OSC
10 MINUTES
10 SECONDS
MINUTES
SECONDS
MINUTES
SECONDS
00 – 59
00 – 59
xxxx8h
W
R
10 CENTURY
CENTURY
CONTROL
00 – 39
xxxx7h
xxxx6h
WDS
AE
BMB4
Y
BMB3
ABE
BMB2
Y
BMB1
Y
BMB0
Y
RB1
Y
RB0
Y
WATCHDOG
INTERRUPTS
?
?
xxxx5h
xxxx4h
xxxx3h
xxxx2h
AM4
AM3
AM2
AM1
Y
Y
10 DATE
10 HOURS
10 MINUTES
10 SECONDS
DATE
HOURS
MINUTES
SECONDS
ALARM DATE
ALARM
HOURS
ALARM
MINUTES
ALARM
SECONDS
01 – 31
00 – 23
00 – 59
00 – 59
xxxx1h
xxxx0h
Y
WF
Y
AF
Y
0
Y
BLF
Y
0
Y
0
Y
0
Y
0
UNUSED
FLAGS
?
?
x = Don’t care address bits.
X = Unused. Read/writeable under write and read bit control.
FT = Frequency test bit.
OSC = Oscillator start/stop bit.
W = Write bit.
R = Read bit.
WDS = Watchdog steering bit.
BMB0–BMB4 = Watchdog multiplier bits.
RB0, RB1 = Watchdog resolution bits.
AE = Alarm flag enable.
Y = Unused. Read/writeable without write and read bit control.
ABE = Alarm in backup mode enable.
AM1–AM4 = Alarm mask bits.
WF = Watchdog flag.
AF = Alarm flag.
0 = Reads as a 0 and cannot be changed.
BLF = Battery low flag.
12
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